This laboratory takes the ESD snapback clamp models from the previous laboratory to simulate the ESD protection of the input and output of a two-stage op amp with PMOS differential input transistors.
The steps for performing the laboratory are given. When the student has completed the laboratory, send Dr. Allen a copy of your results to pallen@ece.gatech.edu and he will send a copy of his solutions for the laboratory.
Lecture Notes for Lesson 8 – Lab02 Simulation of ESD Protection for an Op Amp