This lesson deals with the systems perspective of applying ESD protection. Rail-to-rail and local-clamp based protections schemes are discussed. The physical aspect of ESD circuits is crucial to their performance and the importance of ESD buses and cell connections for HBM and CDM protection are illustrated. Parasitic snapback transistors are discussed. This type of snapback transistor is only seen on the layout and not the schematic.
The tools for ESD protection include calculators such as the ESD R*W calculator for finding the value of the series ESD resistance for a given ESD clamp and a given transistor to be protected. Other tools include simulation using the ESD snapback clamp models developed in the last lesson.
Common mistakes in ESD design are outlined for the purpose of making the design aware of ESD pitfalls.
Lecture Notes for Lesson 6 – ESD System Protection and Tools