This lesson presents a simple SPICE simulation model for ESD snapback clamps that allows the analog designer to simulate the performance of the ESD protection circuit. Up to this point, simulation of ESD snapback clamps required complex models developed by model specialists. A simple snapback model is developed for ESD clamps that are not sensitive to the rate of rise of the ESD voltage. This model has been improved to be sensitive to the rate of rise of the ESD voltage.
Steps are shown how to develop the two models from the IV characteristics of the ESD snapback clamp. Examples of applying the snapback clamp models to find the results of ESD output protection circuits and ESD input protection circuits. The simulation capability provides the means of determining the ESD series resistor necessary to protect the analog transistors.
These models will be used in Lessons 7 and 8 which are laboratories to apply the ESD snapback clamp models to obtain the simulation performance of output and input ESD protection circuits.
Lecture Notes for Lesson 5 – ESD Simulation of ESD Clamps